Part 8: Timing – RTL Design Success

Author: Craig Maiman – Principal RTL Design Consultant

Welcome to the RTL Design Success series — Part 8 of 9

6.5 Timing

Meeting performance and timing requirements can be a time-consuming process – if it is too easy, then you’re either not pushing the technology enough or you are not using the appropriate process node for your design performance requirements (so, you’re making the design more expensive than it needs to be).

I see many designers that take no heed to how many levels of logic they’re coding and are hoping that the synthesis engine will just take care of everything to meet timing.  Synthesis can do amazing optimizations, but if the logic is just too far off in timing, no amount of synthesis runs will fix it.

When I first started coding FPGAs in the early 1990s, it was very slow technology, and you would be very lucky to get more than a few levels of logic between registers – so a constant attention to how many of levels of logic were being created was necessary.  Of course, you still need to – there’s just more levels of logic available than those days.

So, keep timing in mind from the very beginning, not as an after-thought.  Also, be very careful with your timing constraints, in particular false path constraints, which can really bite you if incorrectly applied.

An example would be an asynchronous FIFO.  While it would be tempting to create a false path between the clock domains on either side of the FIFO, that would be a mistake as it could cause functional failure in a production chip.  Many asynch FIFOs rely on Gray coding internally and applying a false path between the two FIFO clocks could create excessively long paths between the domains resulting in more than 1 bit changing at a time.

An excellent paper on asynchronous clock constraining and in particular FIFOs can be read here.

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