Part 7: Assignments – RTL Design Success

Author: Craig Maiman – Principal RTL Design Consultant

Welcome to the RTL Design Success series — Part 7 of 9

6.3 Default Assignments

Whenever you have a process block (both sequential and combinatorial) you run the risk of creating unintentional loops.  Particularly if you have conditional statements in the process.

The best way I’ve found to avoid these is to have default assignments at the beginning of the process block.  Doing it this way you only need to specify the places where the signals get asserted, not having to worry about all the conditions where they are not.

A code snippet showing this:

always_comb begin

      // Defaults

      frame_fifo_rd         = 1’b0;

      hdr_w0_wen            = 1’b0;

      hdr_w1_wen            = 1’b0;

      hdr_w2_wen            = 1’b0;

      hdr_w3_wen            = 1’b0;

      unique case (current_state)

        `FEF_PREP_IDLE     : begin

           if ( !frame_fifo_empty && !soft_resetq ) begin

              frame_fifo_rd = 1’b1;

              next_state    = `FEF_PREP_HDR_IN0;

           end

           else next_state  = `FEF_PREP_IDLE;

        end

        `FEF_PREP_HDR_IN0    : begin             // W0 at FIFO output

           hdr_w0_wen       = 1’b1;              // Save W0

           if ( !frame_fifo_empty ) begin

              frame_fifo_rd = 1’b1;              // Get the next word

              next_state    = `FEF_PREP_HDR_IN1;

           end

           else next_state  = `FEF_PREP_HDR_IN0;

        end

6.4 Instrument Your RTL

When running a unit-level testbench, especially when running long randomized tests, I have often found it useful to instrument my code so that I can more easily debug issues (Only turn these on when actively debugging an issue, so your log file doesn’t blow up).  It can also be useful to see what randomized tests do to the state flow and patterns of behavior of the unit under test.

Trying to sort through hours of waves and thousands of signals may be intractable, so instrumenting the code can be extremely useful.

Instrumenting can be as simple as printing out what state a FSM is in or if a certain combination of signals and/or states is detected.  As you get closer to a bug, your instrumenting can get more specific.

Here is example of instrumentation:

   always_ff @(posedge clock) begin

      if (opb_tmr_timer_info_q3.valid && opb_tmr_timer_info_q3.remove_match_a)

$display($time, ”  Instance %m  OPB TIMER:        REMOVE Match on A for Addr(CID/SEQ#): %h”, opb_tmr_timer_data_q3.address);

      if (opb_tmr_timer_info_q3.valid && opb_tmr_timer_info_q3.remove_match_b)

$display($time, ”  Instance %m  OPB TIMER:        REMOVE Match on B for Addr(CID/SEQ#): %h”, opb_tmr_timer_data_q3.address);

      if (opb_tmr_timer_info_q3.valid && opb_tmr_timer_info_q3.restart_match_a)

$display($time, ”  Instance %m  OPB TIMER:        RESTART Match on A for Addr(CID/SEQ#): %h”, opb_tmr_timer_data_q3.address);

      if (opb_tmr_timer_info_q3.valid && opb_tmr_timer_info_q3.restart_match_b)

$display($time, ”  Instance %m  OPB TIMER:        RESTART Match on B for Addr(CID/SEQ#): %h”, opb_tmr_timer_data_q3.address);

if (opb_tmr_timer_info_q3.valid && (opb_tmr_timer_info_q3.change_to_get_match_a || opb_tmr_timer_info_q3.change_to_get_match_b))

$display($time, ”  Instance %m  OPB TIMER:        CGT Timer for Addr(CID/SEQ#): %h”, opb_tmr_timer_data_q3.address);

   end

An example of testbench output from instrumenting:

105300  Instance opb_tb.opb_top_inst.opb_buffer_inst OPB BUFFER:       Req:  1   Resp: 1   Src: 0   Addr(CID/SEQ#): 01011111   Data.cqid: feed   Data.swtag: 0000000000000000   Data.isget: 0   Data.isack: 0   Data.wfgd: 0

118300  Instance opb_tb.opb_top_inst.opb_buffer_inst OPB BUFFER:       Req:  1   Resp: 1   Src: 0   Addr(CID/SEQ#): 01011112   Data.cqid: feed   Data.swtag: 0000000000000000   Data.isget: 0   Data.isack: 0   Data.wfgd: 0

Of course I also recommend the usage of SystemVerilog Assertions for checking protocols and detecting illegal conditions and transitions.

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