Part 4: Testbench Flow – RTL Design Success

Author: Craig Maiman, Principal RTL Design Consultant

Welcome to the RTL Design Success series — Part 4 of 9

5.4 Typical Flow of a Testbench

An example of a simple testbench would have a main process which executes sequentially that just does writes and reads of some registers and would call procedures to do those actions.

So, the testbench would consist of the instantiations of the DUT, BFMs, etc. and a main process for sequencing through the stimulus.  Of course, if you have multiple independent interfaces, then you’d typically have multiple stimulus processes.

For more complex testbenches your stimulus process may call more complex procedures to do whole tests and not just simple register accesses.

A simple testbench main process may be as follows (pseudo code):







Whereas a more hierarchical, complex testbench flow could be as follows:

Main: Process






Function Directed_tests





Function Test1





Note that testbench code need not adhere to any synthesizable code restrictions – anything goes!  Of course, within the bounds of any development team coding guidelines.

5.5 Self-Checking Testbench

While the above simple testbench is self-checking in the sense that the designer doesn’t need to hand-check the results, more complex testbenches can be developed which have predictive logic checking the RTL outputs.

In a typical self-checking testbench the stimulus processes may load testbench FIFOs with information that can be used on the output side for the self-checking logic.  For example, if you know that a certain request going into your RTL should cause a certain output sequence, you could load a FIFO with a few bits of information indicating what to expect.  Like a particular register read request going into your block should cause 3 writes, then load the testbench FIFO with a code that indicates “Expect 3 writes”.  This FIFO entry would be read by the self-checking logic and would know to expect 3 writes.  If the expected 3 writes come out then your self-checking logic could print “Read Req Success” or if the output does not meet what’s expected, it could print “Read Req Failure”.  In that case you’d probably want to simulation to stop.

A recent testbench I developed had 4 independent stimulus processes and at least 6 FIFOs with some of them going between stimulus processes because there was a dependence between what they would be inputting into the block.

It’s worth doing runs where your randomized portion runs for hours.

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