The XtremeEDA engineering team has developed significant strengths though our frequent work with on-chip and chip-to-chip interface protocols used across the semiconductor industry. We see them from the bus point of view through bridges, switches and interconnects. We also work on the end-point bus transactors and SoC peripherals. PCIe is one protocol where XtremeEDA has extensive experience, including with San Diego, California – based John Pabisz and Mike Schaecher.
From their time at Sun Microsystems and more recently Oracle, John and Mike came to XtremeEDA as legitimate PCIe experts. Dating back to 2008 and 2003 respectively, with a combined experience of more than 20 years, they’ve seen PCIe from every angle.
Mike remembers back to how his involvement with PCIe started through a stroke of luck in 2003…
Our company was trying to figure out the future of IO in general. The decision was made to use Infiniband as our standard. After working on that for about six months, management did a 180, deciding instead that PCIe was the way to go. So started my first work with PCIe 1.0.
Fast forward to 2016. With 14 years of experience, Mike recounts some of the trials and tribulations of working with a complex protocol like PCIe…
This was from the most recent project where John and I worked together. Just as we were nearing DV complete, the device architecture changed: 3 new PCIe ports and x2 capability. Fortunately we designed our UVM testbench to be extensible enough to absorb the changes with only minor impact. Within a few days I was already filing bugs on the x2 link width additions; two weeks later all the changes and additions were being exercised; and within 3 weeks, most of the tests were running in our random regression. The late architectural change put us in a tough spot and I was really proud of how we pulled that together.
Looking back at his experience, John sees PCIe as just one part of what he does well…
I’m a motivated guy. I’ve been around PCIe long enough to build a deep understanding of the full stack covering all of the transaction, data-link and physical layers. I’ve worked on the PHY and SERDES, with Cadence and Synopsys verification IP and used multiple verification methodologies: UVM, VMM, straight SystemVerilog, Vera and even C++! Definitely consider myself tenacious when it comes to root-causing problems and I’ve grown into a strong leader. Of course PCIe is my specialty, but the skills I learned along with it are what count for me. Flexibility, being able to adapt to situations as development objectives change, those are the things that come with the experience. It helps me do more than just PCIe.
Mike echoes John’s experience in many respects…
I’ve had opportunities to work on gen1, 2, 3 and 4 protocols. I’ve worked with the best PCIe VIP vendors in Denali, Cadence, and Synopsys. Our benches were always state-of-the art using Vera, VMM and UVM. I’ve enjoyed really getting into the details of the spec, even finding bugs that escape some of the vendor checks. As far as teams go, John and I have worked together for about 10 years. He spent the first 8 of those years in Boston area until I finally convinced him the weather is better in San Diego! We’re happy to bring our expertise to XtremeEDA and we’re looking forward to leading teams for clients developing PCIe enabled devices. Of course we’re also ready for the challenge of supporting any other IO protocols clients might put in front of us!
John and Mike are at XtremeEDA to lead PCIe verification teams, but our PCIe expertise doesn’t end with them. The Toronto, Ontario based duo of Bo Qin and David Liu provide a perfect, ready-made PCIe verification team; likewise for Dave Read and Davis Miller from the Portland, Oregon area. All are capable of leading teams throughout North America.
If your next device is PCIe enabled or your SoC subsystem needs a team of highly experienced verification engineers to push it through to tape-out, John Pabisz, Mike Schaecher, our Toronto and Portland teams and the entire XtremeEDA engineering staff are ready for the challenge.
A Template For Evaluating Portable StimulusSeptember 24, 2018
by Neil Johnson, Chief Technologist I’ve written a lot about portable stimulus over the last year, all of it being theoretical. […]Learn More
UVM Reuse: How to use a non-UVM VIP in a UVM environmentAugust 14, 2018
by Ramprasad Chandrasekaran, Principal Verification Consultant What are we talking about? We as a verification community like to talk about creating […]Learn More
Video: Building An Integrated Verification FlowJuly 31, 2018
by Neil Johnson, Chief Technologist DAC2018 has come and gone. It was a great conference as usual with lots of […]Learn More
UVM Gotchas: UVM Register Layer Prediction ModesJuly 17, 2018
by Robin Hotchkiss, Senior Verification Consultant What are we talking about? This post talks about the difference between implicit and […]Learn More