Verification Methodology Manual (VMM)
Our VMM training module provides everything that you, the verification professional, needs to get started in creating advanced, constrained-random, coverage-driven, self-checking testbenches using the VMM set of SystemVerilog class libraries. This course details the advanced concepts of testbench architecture, communication and run-flow as well as how to use the power of the SystemVerilog language, and VMM specifically, to create effective, reusable verification environments.
Course Outline
- VMM Overview and Benefits
- Environment Abstraction Layers
- Data and Transaction Modeling
- Inter-object Connectivity
- Static Environment Components
- Stimulus Generation
- Message Service Interface
- Environment Construction and Run-Flow
- Environment Customization and Error Injection
- Typical Testcase Examples
Lab Exercise: A complete VMM-based verification environment.
Duration: 1 day
Dates & Locations:
- Please contact learn@xtreme-eda.com for more information.