Verilog 2001: New Capabilities
90% Lecture, 10% Pencil-and-Paper Exercises
Basic Level
This course was created by, and will be delivered by TM Associates, Inc.
This one-day Verilog-2001 seminar shows design, verification, and support engineers how to apply the latest IEEE Std 1364-2001 syntax, in the context of real-world SOC development. It's also an effective way to update the skill set of engineers who've picked up Verilog "on-the-job," with little or no actual training.
Unlike many Verilog workshops which focus on dry syntax, this seminar is rich in practical design examples, insights into Verilog semantics, and tips to avoid hidden pitfalls. The eight-hour seminar is primarily lecture. To vary the pace and reinforce the material, various pencil-and-paper exercises ask the attendee to complete or debug segments of code in the workbook. Answers will be displayed on the screen. To fully utilize the time invested, this seminar does not attempt to cover every enhancement in detail, but focuses on the 80% of Verilog-2001 features most useful to today's SOC engineers.
Because Verilog is a rapidly-evolving language, the 2001-oriented material is interspersed with brief look-ahead references to anticipated SystemVerilog changes. For example, the material on Verilog-2001 @(*) sensitivity lists is followed by a glimpse at the SystemVerilog keywords always_comb and always_ff @(...).
Attendees will take back a concise appendix of Verilog-2001 constructs for later reference, as well as Coding Guidelines for synthesis and for verification.
Benefits
Upon completion of this course, students will:
- Learn the most useful syntax of Verilog 2001
- Learn higher-level description of synthesizable modules
- Understand enhanced verification capabilities of Verilog 2001
- Learn new simulator and compiler directives
- Get a glimpse of upcoming SystemVerilog enhancements
Intended Audience
Design, verification, and applications engineers who already know Verilog but need to learn the enhanced capabilities in Verilog 2001.
Prerequisites
A working knowledge of Verilog.
Suggested follow-on course
Advanced Verilog 2001 Coding Styles for Synthesis & Verification - 3 days
Verilog Verification Methodologies - 3 days
Training Approach
This is an intensive, interactive course, which is approximately 90% lecture and 10% pencil-and-paper exercises. Questions are highly encouraged.
Course Outline
Unit_1: Key Syntax Enhancements
Focus on basic, syntax-oriented changes to language:
- Evolution of Verilog Language
- How Verilog-2001 Meets SOC Challenges
- C-Style Port Declarations
- Sensitivity Lists: @(*)
- Indexed Part-Select Case Study:
- Subset-Decoder Example
- In-Line Initialization Case Study: Pitfall: Initialization Races
SystemVerilog:
always_comb, always_latch, always_ff
Unit_2: Synthesis-Specific Enhancements
Many of Verilog-2001's enhancements enable higher-level description of synthesizable modules--particularly using signed arithmetic:
- Width Extension Rules
- Implicit Scalar Nets
- 2-D Array Case Study: RGB Video Frame
- Generating I/O Pad Cells
- Signed-Arithmetic Case Study: Signed-Multiplier Example
- Arithmetic Right-Shift (>>>)
- Signed Literal Vectors (s)
- Conversion Functions $(un)signed
- Tool-Specific Attributes (* *): Full-Case/Parallel-Case Demystified
SystemVerilog: Semantics of unique and priority if and case Pencil-and-Paper Exercise: Code a memory having bit-select capability.
SystemVerilog:
RGB video frame revisited, using struct
Unit_3: Complex IP Support
A key goal of Verilog-2001 is to enable synthesis and verification of complex, parameterized IP cores:
- 3-D Array Case Study: MPEG Data Compression
- Parameters and Redefinition
- C-Style Functions and Tasks
- Generate-Loop Case Study: Triangular-Sort Array
- Using localparam and Constant Functions
- Automatic-Function Case Study: Synthesizable, Recursive Number Generator
Pencil-and-Paper Exercise:
Code a constant function to derive a localparam.
SystemVerilog:
Function return statements and void functions.
Unit_4: Verification-Specific Enhancements
Verilog-2001 overcomes limitations of Verilog-1995, and facilitates verification of deep-submicron, system-on-chip designs:
- New Simulator Options ($plusargs)
- Standard Random-Number Case Study: Randomized Read/Write RAM BFM
- New Compiler Directives ('file, etc.)
- File I/O Case Study: File-Driven Keypad Stimulus BFM ($fscanf, etc.)
- Deep-Submicron Timing Checks (pulsestyle_on*)
- Enhanced SDF File Support ($sdf_annotate)
- Verilog configuration Case Study
SystemVerilog:
The interface Block
Pencil-and-Paper Exercise:
Write BFM (bus-functional model) for randomized ATM packets.
SystemVerilog:
Assertion-Based Testing Concepts.
App A: Verilog-2001 Enhancements
App B: Synthesis Guidelines at a Glance
App C: Verification Guidelines at a Glance
Dates & Locations:
- Please contact learn@xtreme-eda.com for more information.