System Verilog Assertions (SVA): Introduction
The course provides an introduction to SystemVerilog Assertion (SVA). At the end of this hands-on course the student should be familiar with value of SVAs in a modern functional verification environment. This course combines tutorial with hands-on labs that reinforce the techniques learned in the tutorials.
This course can be combined with our SVA: Advanced Methodology course and tailiored for your company's needs.
The course provides the following practical knowledge for your verification and design engineers:
Verification Methodology Overview
- Constrained Random Generation
- Automated Checking
- Data checking
- Temporal Assertions
- Total Coverage Analysis
- Typical Verification Environment Structure
- Generators, Drivers, Monitors
Assertion Overview
- Benefits of assertions
- Bug localization
- Spatial and temporal
- Rapid debug
- Formal Verification Tools
- Who writes assertions?
- System Architects
- Designers
- Verification Engineers
SystemVerilog Overview
- Introduction of new objects and data types useful in assertions
SystemVerilog Assertions (SVA)
- Immediate Assertions
- Concurrent Assertions
- System Tasks and Failure Messages
- $rose, $fell, $onehot, $countones, $unknown, $fell, $stable
- $fatal, $error, $warning, $info
- Sequences
- Methodology: building blocks to create larger expressions
- Declaring Basic Sequences
- Sequence Operators
- Concatenation and repetition operators
- and, or operators
- introduction within, intersect, throughout, etc.
- Assert statement
- assume/cover constructs
Properties
- Basic Property syntax and declaration
- not, and, or operators
- Implication
- Overlapping
- Non-Overlapping