System Verilog Assertions (SVA): Advanced Methodology
Building on the fundamentals learned in our SVA: Introduction course, this more advanced course expands in greater detail and focusses on the fundamentals of using the SVA to solve real-world issues. This course combines tutorial with hands-on labs that reinforce the techniques learned in the tutorials.
This course can be combined with our SystemVerilog Assertion: Introduction course and tailiored for your company's needs.
The course outline includes the following:
Assertion Development
- Identification of assertion targets
- Metavalue (X, Z)
- Protocol (Interfaces in the design)
- Transactions
- Common antecedent
- Guarding techniques
Debugging Assertions
- Waveform Viewers
- Tips and Tricks
- Common Pitfalls
- Excessive thread launching
- Oversampling
- Profiler Usage (SV Simulator depedant)
- White paper methods
Advanced Sequence and Property Usage
- Variables and parameterized sequences
- Executing statements upon successful completion of a sequence
- Expect statement
- Inference of clocking events and iff conditions
- Multiclock statements
- Recursive Properties
- Deeper examination of the repetition, within, intersect, throughout
- File partitioning and management?
- Encapsulation of assertions
- Interfaces
- Modules