Modeling and Verification With SystemC
This four-day workshop introduces the student to modeling and verification with C/C++ and the SystemC C++ class library including the SystemC Verification library (2.0-SCV). It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC with a modeling and verification focus. Version 2.0 and SystemC Verification Library concepts are taught.
SystemC Functional level and transaction Level (TLM) modeling is covered. Communication refinement methodology and techniques are covered in depth. SystemC Verification concepts are taught. The student will learn how to write, compile, execute and debug system and hardware descriptions with SystemC
This course is mixed lecture and exercises, with an exercise for nearly every topic.
Prerequisites
- Strong familiarity with Verilog, VHDL or C (at least one)
Related Courses
Course Outline
- Introduction
- SystemC modeling
- Basic modeling structure
- Getting started - running & debugging
- C++
- Streams, pointers and references, data abstraction
- Data hiding, initialization & cleanup
- Inheritance, overriding, overloading, const, templates, polymorphism
- Libraries (STL, BOOST)
- Modules
- Ports, Interfaces, & Channels
- Module constructor
- Events
- Processes in general
- Thread processes
- Method processes
- Module instantiation (in modules)
- sc_main
- Channels
- Time & clocks
- Module instantiation (in sc_main)
- Simulation functions
- SystemC data types
- Primitive channels
- User defined channels
- Communication refinement
- Channel refinement & adapter
- SystemC Verification
- Data instrospection
- Randomization
- Constraints
- Customizing data generation
- Sparse arrays
Duration: 4 days
Dates & Locations:
- Please contact learn@xtreme-eda.com for more information.