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Office: 508-845-1590
Cell: 508-735-9929
jnash@xtreme-eda.com

XtremeBoost::Training

System Verilog for Verification Professionals™

A three-day course providing the verification professional everything they need to create advanced constrained-random, coverage-driven, self-checking testbenches in SystemVerilog.

Modeling With SystemC

This four-day workshop introduces the student to modeling and verification with C/C++ and the SystemC C++ class library. It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC with a modeling focus.

Modeling and Verification With SystemC

This four-day workshop introduces the student to modeling and verification with C/C++ and the SystemC C++ class library including the SystemC Verification library (2.0-SCV). It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC with a modeling and verification focus. Version 2.0 and SystemC Verification Library concepts are taught.

A two-day course building on the concepts and methodologies from our System Verilog for Verification Professionals course to further elaborate on the elements of an Advanced Coverage Driven Verification (CDV) methodology.

System Verilog Assertions (SVA): Introduction

This course provides fundamentals of the SystemVerilog Assertion (SVA) language. At the end of this course you'll learn the SVA syntax, and through hands-on labs how to create immediate or concurrent assertions, basic sequences, and more. This course and our SVA: Advanced Methodology course can be combined.

SystemVerilog Assertions (SVA): Advanced Methodology

Bulding on the fundamentals of our SystemVerilog Assertions: Introduction coures, this course explores more advanced topics and methodologies such as best practices to develop SVAs, debugging assertions, and building advanced sequences. The hands-on labs and exercises ensure that you immediately try working what you have learned.

C++ for the HDL Engineer

This 2 day class is intended for the Verilog/VHDL engineer or C programmer who will be using C++ for modeling hardware or systems using C++, or C++ based languages such as SystemC.

Advanced SystemC

This 2 day advanced SystemC class aims at experienced SystemC users desiring to take their use of the language to a higher level. Emphasis is placed on modeling and writing custom channels.

Advanced SystemC with SCV

This 2 day advanced SystemC class aims at experienced SystemC users desiring to take their use of the language to a higher level. Emphasis is placed on verification elements and advanced models including writing custom channels.

Verification Methodology Manual (VMM)

This one-day course gives you everything you'll need to create a reusble functional verification environment using the guidelines and library of components found in the Verification Methodoloay Manual (VMM).

Managing R&D Projects

Provides managers and project team members with the necessary tools they need to achieve project and corporate success.

Verilog 2001: New Capabilities

A one-day course showing engineers how to apply the Verilog 2001 (IEEE Std 1364-2001) syntax using real-world practical examples.

Verilog 2001: Introduction

A two-day course providing a complete introduction of the Verilog 2001 (IEEE Std 1364-2001) for design and verification.

Verilog 2001 for HW Designers

A four-day hands-on detailed investigation into using VHDL for design and verification.

Verilog for Experienced VHDL Designers

A three-day course providing projects providing designers experienced in VHDL with all they need to master the Verilog language.

Verilog Verification Methodologies

A three day hands-on course using Verilog to create reusable verification environments.

Advanced Verilog 2001 Coding Styles

A three day hands-on course providing Verilog 2001 coding techniques for correct and efficient synthesis and simulation.

Introduction to Digital DFT

This 2-day course provides an introduction to Digital Design For Test (DFT). At the end of this course the student should be familiar with basic DFT structures in advanced chip design.

Advanced Digital DFT

This 1-day course is aimed at experienced designers who desire to know more about DFT architecture and trade-offs. At the end of this course the student will be familiar with advanced DFT architectures in complex chip designs.

This 1 day course provides an introduction to Analog and Mixed-signal (DFT). At the end of this course the student will be familiar with basic analog and Mixed-signal DFT structures used in advanced chip designs.

This half day course provides an introduction to new the IEEE DFT specifications. At the end of this course the student will be familiar with these new DFT specifications, which can be applied to advance chip designs.

Specman Elite Verification Methods

This day course provides an excellent introduction to the use of Specman e language along with the methodologies from experienced methodologists to ensure your success.

VHDL Introduction

A two-day introductory course in the VHDL language to learn how to capture behavioural models and simulate functional behaviour.

VHDL for Hardware Designers

A four-day hands-on detailed investigation into using VHDL for design and verification.

Advanced VHDL Coding Styles

A three day hands-on course delving deeper into VHDL techniques for synthesis and verification.