XtremeEDA's industry renowned consultants excel in functional yield enhancement, a discipline rigorously applied to all aspects of the design process, particularly Electronic System Level (ESL) modeling, verification and design for testability (DFT). A total commitment to functional yield enhancement assures customer success.
We are industry leaders and innovators in the field of ESL modeling. Our team of experts can help you create SystemC solutions for architectural modeling, hardware and software co-design, and realization of Behavioral and RTL designs.
Our consultants live and breathe coverage-driven, constrained-random and assertion-based verification. They offer insight into the essential methodologies at the core of a modern HVL-based (Hardware Verification Language) verification strategy, and have extensive domain knowledge in the following areas:
- Networking devices and protocols
- Video and graphics processors
- Embedded processors
- Cryptography
- DFT
- Interconnect Protocols
XtremeEDA's talented multi-lingual team is fluent in and adept at translating between all of the following languages:
- SystemVerilog
- C++ and SystemC
- OpenVera
- Specman/e
- VHDL
- Verilog
The engagement model we use is carefully tailored to our customers' requirements. Whether it is a short, intense methodology infusion provided by an XtremeBoost or a long-term project, we assemble the right team for your needs. Following are some examples of past assignments:
- Verification and design project involving multiple generations of a high volume consumer product video processing ASIC. Design coded in VHDL with Specman/eused for verification The coverage-driven verification environment was eVC based. Third party IP was utilized where available, such as an OCP eVC for checking an OCP standard memory interface. Design IP includes an ARM processor. Behavioural model development was also performed using C++.
- Verification of ATM over MPLS origination and termination in two data path FPGAs used in an OC48 linecard. Existing techbenches were completely reworked and new testcases added.
- A powerline (Homeplug AV) networking adapter chip with an embedded ARM processor and external MII, PCI, and MPEG Transport Stream interfaces. OpenVera used for verification following an RVM approach building a self-checking coverage-driven constrained-random environment.
- Verification of an algorithmic CAM supporting - through different flavours of the chip (gate count around 3 million with a very large configuration space) - two different sets of proprietary interfaces. OpenVera NTB/RVM with functional coverage used to generate constrained-random test cases.
- Development of an abstract and reusable transaction level model in VHDL for use in a massively parallel reconfigurable compute engine.
- DBIST (deterministic BIST) implementation on a 15M gate telecommunications ASIC. Multiple BIST controllers handled a set of 2560 scan chains for stuck-at and transition fault testing (with multiple clock domains). JTAG controlled DFT also included boundary scan (with high-speed serial links), memory BIST for repairable RAMs, and optional reconfiguration of scan chains into standard structure of over 80,000 elements each.