OTTAWA, Canada, 11 April 2008
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today announced the Best Paper Awards for the 18th annual Synopsys Users Group (SNUG(R)) San Jose, held March 31 -- April 2, 2008, in Santa Clara, CA.
A record-breaking 2,032 users attended SNUG San Jose, a 29 percent increase in participants over SNUG 2007. The conference featured 40 technical presentations and 32 tutorials, plus demos, panels and vision sessions, all presented by more than 160 Synopsys users and experts to fellow design engineers.
The Technical Committee Award went to the team of Noah Aklilu of Cisco Systems, Inc., and Anthony Redhead of XtremeEDA Corp. for, "Getting Synchronous Resets Right!"
Source San Francisco Business Times
OTTAWA, Canada, 21 January 2008
XtremeEDA today announced that their VP, Engineering Bryan Morris will be presenting a free SystemVerilog for Verification tutorial in Ottawa on Tuesday February 26th, 2008.
The tutorial provides an introducton to the SystemVerilog language features that are needed to create a constrained random, coverage driven verification environment. These are some of the concepts you'll learn in this tutorial:
- New Data Types: logic, strings, classes structs, arrays, enumerations, etc.
- Object Oriented Programming (OOP)
- core principles of OOP: encapsulation; inheritance; polymorphism;
- definition;
- class construction;
- Data Hiding
- Arrays and Queues
- Interfaces and modports
- Clocking and Program Blocks
- Constrained Random Stimulus Generation
- SV constraints: simple, implicit, iterative, weighted distribution, function calls;
- in-line and out of line constraints;
- random stability;
- Intelligent Automated Self Checking
- data checks: transaction validation;
- temporal checks: time-consuming;
- scoreboarding architectures;
- SystemVerilog Assertions.
- Total Coverage Analysis: Functional Coverage.
- Coverage Driven Verification (CDV)
- Other language features;
- Methodologies: VMM, OVM, Others
This presentation will be held at the Holiday Inn Select in Kanata.
Please RSVP by February 22nd to learn@xtreme-eda.com with your name and contact details.
OTTAWA, Canada, 19 January 2008
XtremeEDA today announced that one of their Principal Engineers, David Jones will be presenting a paper entitled "VFlect: Effortless Object Interoperability Between C++, SystemC and SystemVerilog" at the upcoming DVCon conference being held February 19-21 in San Jose.This paper describes VFlect, a system that facilitates object communication between C++, SystemC and SystemVerilog. Given an interface definition written in a variant of the CORBA IDL, VFlect generates the required stubs and libraries to support cross-language method calls and object transport. The VFlect libraries use standard IEEE 1800 DPI-C library features; no proprietary features are required in the simulator. Although the current system supports SystemC and SystemVerilog, there is no reason why support for other hardware verification languages could not be added.
DVCon presentation details can be found here
OTTAWA, Canada, 23 November 2007 - XtremeEDA has moved into their new, bigger Ottawa office.
XtremeEDA has grown beyond their current facilities in Ottawa and has moved to their new spacious office closer to the downtown of Ottawa. This new office provides XtremeEDA with the ability to expand their ASIC/FPGA functional verification and DFT practices.
Effective December 3rd, 2007, XtremeEDA's new office is located at:
201-1339 Wellington
St. West
Ottawa, Ontario
Canada
K1Y 3B8
OTTAWA, Canada, 7 February 2007 - XtremeEDA is now registered with Canada's Controlled Goods Program (CGP).
The CGP program is managed under the Canada Defense Production Act and is recognized by other nations under ITAR regulations. This registration allows XtremeEDA to work on ITAR controlled goods and technology. From time-to-time, clients may need a services provider to work on ITAR related technology. XtremeEDA is now ready to help you in that regard.
OTTAWA, Canada, 6 February 2007 - XtremeEDA today announced they will be presenting a tutorial, entitled VMM For Dummies authored by Amre Sultan and Dr Hans van der Schoot, at the upcoming SNUG San Jose conference, to be held April 2-4 in Santa Clara, CA.
The tutorial illustrates how to develop a VMM-based verification environment with the most commonly used VMM components. Drawing from real project experiences applying the various VMM principles, it walks through the construction of a complete VMM-based testbench for a Rock-Paper-Scissors game, addressing the following questions.
- What are a transaction and a transactor?
- What is a VMM channel?
- What does a VMM-based environment look like?
- What is the built-in run flow?
- How do I implement functional coverage and customize stimulus?
By attending the tutorial verification engineers will be well equipped to hit the ground running on their next VMM-based verification project.
The same authors, as well as another of our Principal Engineers - Dr. Pierre Girodias, are also presenting a paper called Stepping-Up to Scenarios in VMM. The paper illustrates the use of transaction scenarios in VMM for the generation of complex stimulus in a constrained random verification environment. Using a simple riddle as an example, typical design verification issues related to stimulus generation are identified and practical solutions are suggested.
More information can be found here.
OTTAWA, Canada, 4 February 2007 - OTTAWA, Canada, 4 February 2007 - XtremeEDA today announced that one of their Principal Engineers, Dr. Pierre Girodias will be presenting a paper co-authored by himself, Dr Hans van der Schoot and Amre Sultan, entitled Advanced Stimulus Generation Using Scenarios at the upcoming DVCon conference being held February 21-23 in San Jose.
The paper explores the use of transaction scenarios for the generation of complex stimulus in a constrained random verification environment. Using a simple riddle as an example, typical design verification issues related to stimulus generation are identified and practical solutions are suggested.
More information can be found here.