Papers
The Use of Advanced Verification Methods to Address DO-254 Design AssuranceAuthors: J. Keithan, D. Landoll, P. Marriott and Bill Logan
This paper covers a project that is using advanced functional verification methods to verify a RTCA DO-254/EUROCAE ED80 Level A/B design. These methods include Constrained Random Simulation, Design Intent Specification (designer-added assertions), the Total Coverage Model (Unified Coverage Database), and Formal Verification (formal model checking). The project is a real design currently being developed at Rockwell Collins
Authors: David Jones
This paper describes VFlect, a system that facilitates object communication between C++, SystemC and SystemVerilog. Given an interface definition written in a variable of the CORBA IDL, VFlect will generate the required stubs and libraries to support cross-language method calls and object transport. The VFlect libraries use standard IEEE 1800 DPI-C library features; no proprietary features are required in the simulator. Although the current system supports SystemC and SystemVerilog, there is no reason why support for other hardware verification languages could not be added.
Authors: N. Aklilu (Scanmetrics), A. Redhead (XtremeEDA), P. Trehan (Synopsys)
Winner of the Technical Committee Award at SNUG San Jose (2008)
This paper discusses the implementation of synchronous resets. We identify the Verilog coding styles recognized by Design Compiler (DC) and the variables that can be used by DC to control this recognition. We will also discuss the structuring of reset distribution to avoid any special handling in PD. We introduce the Tcl functions developed to analyze the reset trees, as well as cover the reporting provided by DC. We will look at the timing impact of reset recognition using both wire-load and topographical synthesis. Finally, we provide some recipes to drive the recognition of synchronous resets by Design Compiler.
Authors: P. Girodias, H. van der Schoot, A. Sultan
This paper explores the use of transaction scenarios for the generation of complex stimulus in a constrained random verification environment. Using a simple riddle as an example, typical design verification issues related to stimulus generation are identifed and practical solutions are suggested.
Authors: A. Sultan, P. Girodias, H. van der Schoot
This paper aims to shed light on how to develop a basic VMM-based verification environment with the most commonly used VMM components. Drawing from real VMM-based project experiences applying the various VMM principles, we provide readers with the most useful things to know about the VMM to hit the ground running on their first VMM-based project. After reading this paper the reader should be able to answer the following questions: What does a VMM-based environment look like? What are a transaction and a transactor? What is a VMM channel? What is the built-in run flow? How do I implement constrained random stimulus generation, and functional coverage? The reader will be able to see through examples how the VMM guidelines are applied. After reading this paper, the user can take advantage of the concepts presented to ensure his first participation in a VMM-based project is both productive and successful.
Autor: A. Sutton
This paper provides an introduction to the SystemVerilog assertion language and a tutorial on writing assertions. Examples are used to explain the concepts of sequences and properties, and the behaviour of several SystemVerilog temporal operators. This example also demonstrates that a bus protocol can be thoroughly verified using assertions.
Authors: P. Marriott, S. Bailey
This paper describes how the coverage constructs in SystemVerilog can be used to architect an advanced CDV environment. The differences between basic item, cross and transition coverage must be understood in order to answer the three most important coverage questions: "What?", "When?", and "How much?".
Authors: H. van der Schoot, J. Bergeron
This paper presents several recommended practices for implementing transaction-level functional coverage in SystemVerilog. The coverage model is implemented within the methodology defined by the Verification Methodology for SystemVerilog, resulting in a number of additional useful implementation techniques.
Author: D. Jones
This paper introduces the verification engineer to the world of object-oriented design patterns. A design pattern is a conceptual model of a solution to an object-oriented programing problem. Patterns describe not algorithms, but ways of organzing ones' code to enhance resuse and comprehension. Although patterns have been part of the software engineering world for some time, they are equally applicable to verification sproblemsin hardware verification languages (HVL). This paper will discuss the motivations for patterns in general, and present three specific exampes of design apttersn as applied to real-world verification problemss. Although code exampes are given in SystemVerilog, they are equally applicable to Vera and e. For engineers migrating to SystemVerilog, design patterns will assist in converting aspect-oriented (AOP) constructs to well-structured object-oriented (OOP) constructs.
Author: D. Jones
SystemVerilog offers an exciting new environment in which to construct testbenches. Language features support constrained random generation, object-oriented programming, assertions, coverage, and more. Verification engineers new to this environment may not know wher to start or how to use these features. This paper presents a complete testbench for verifying a rock, scissors, paper arbitration module, based on a methodology developed at Mentor Graphics and XtremeEDA, aimed at building effective verification environments with minimal complexity. Due to the simplicity of the device under test (DUT) we can present the complete testbench, as it totals fewer than 300 lines of code. The first section of this paper briefly describes the motivations behind the major verification features of the SystemVerilog. The paper then proceeds to present a high-level verification environment and describe the components that comprise it.
Presentations and Tutorials
VMM Register Abstraction LayerAuthors: A. Sultan (XtremeEDA), J. Bergeron (Synopsys)
This San Jose SNUG 2008 presentation provides a detailed view of the usage model of the Verification Methodology Manual (VMM) Register Abstraction Layer (RAL). The RAL provides all the necessary verification components to define and access an ASIC/FPGA's register map. This in-depth tutorial provides a great overview on how to use this valuable new component of the VMM.
Authors: A. Sultan, H. van der Schoot, P. Girodias
This San Jose SNUG 2007 tutorial provides a great overview of the Verification Methodology Manual (VMM) verification components. This presentation identifies the key elements of a reusable verification environment using the VMM library and the SystemVerilog language.
Authors: P. Marriott, H. Van der Schoot
This presentation was given to a Mentor Users' Conference in 2006. It outlines the necesary elements to create a reusable, maintainable verification environment in System Verilog.
Web Seminars
System Verilog for VerificationA seminar with an overview of everything verification professionals need to create advanced constrained-random, coverage-driven, self-checking testbenches in SystemVerilog